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| www..com TJA1043 High-speed CAN transceiver Rev. 01 -- 30 March 2010 Product data sheet 1. General description The TJA1043 is a high-speed CAN transceiver that provides an interface between a Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the automotive industry, providing differential transmit and receive capability to (a microcontroller with) a CAN protocol controller. The TJA1043 is a step up from the TJA1041A high-speed CAN transceiver. It offers improved ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and passive behavior when the supply voltage is turned off. Advanced features include: * Low-power management controls the power supply throughout the node while supporting local and remote wake-up with wake-up source recognition * Several protection and diagnostic functions including bus line short-circuit detection and battery connection detection * Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V These features make the TJA1043 the ideal choice for high speed CAN networks containing nodes that need to be available all times, even when the internal VIO and VCC supplies are switched off. 2. Features and benefits 2.1 General Fully ISO 11898-2 and ISO 11898-5 compliant Suitable for 12 V and 24 V systems Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI) VIO input allows for direct interfacing with 3 V and 5 V microcontrollers SPLIT voltage output for stabilizing the recessive bus level Listen-only mode for node diagnosis and failure containment 2.2 Low-power management Very low current Standby and Sleep modes, with local and remote wake-up Capability to power down the entire node while supporting local, remote and host wake-up Wake-up source recognition Transceiver disengages from the bus (zero load) when VBAT absent Functional behavior predictable under all supply conditions www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 2.3 Protection and diagnosis (detection and signalling) High ESD handling capability on the bus pins Bus pins and VBAT protected against transients in automotive environments Transmit Data (TXD) dominant time-out function with diagnosis TXD-to-RXD short-circuit handler with diagnosis Thermal protection with diagnosis Undervoltage detection and recovery on pins VCC, VIO and VBAT Bus line short-circuit diagnosis Bus dominant clamping diagnosis Cold start diagnosis (first battery connection) 3. Ordering information Table 1. Ordering information Package Name TJA1043T SO14 Description Version plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 Type number TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 2 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 4. Block diagram VIO VCC VBAT 5 3 VCC 10 TJA1043 TEMPERATURE PROTECTION 13 VIO SLOPE CONTROL + DRIVER CANH TXD 1 TIME-OUT 12 CANL VBAT WAKE 9 ERR_N STB_N 8 14 MODE CONTROL + WAKE-UP CONTROL + ERROR DETECTION 11 SPLIT VBAT SPLIT 7 6 INH EN RXD 4 MUX + DRIVER WAKE-UP FILTER 2 GND 015aaa061 Fig 1. Block diagram TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 3 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 5. Pinning information 5.1 Pinning TXD GND VCC RXD VIO EN INH 1 2 3 4 5 6 7 015aaa062 14 STB_N 13 CANH 12 CANL TJA1043 11 SPLIT 10 VBAT 9 8 WAKE ERR_N Fig 2. Pin configuration 5.2 Pin description Table 2. Symbol TXD GND VCC RXD VIO EN INH ERR_N WAKE VBAT SPLIT CANL CANH STB_N Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description transmit data input ground supply transceiver supply voltage receive data output; reads out data from the bus lines supply voltage for I/O level adaptor enable control input inhibit output for switching external voltage regulators error and power-on indication output (active LOW) local wake-up input battery supply voltage common-mode stabilization output LOW-level CAN bus line HIGH-level CAN bus line standby control input (active LOW) 6. Functional description The TJA1043 is a stand-alone high-speed CAN transceiver with a number of operating modes, fail-safe features and diagnostic features that offer enhanced system reliability and advanced power management. The transceiver combines the functionality of the TJA1041A with improved EMC and ESD capability and quiescent current performance. Improved slope control and high DC handling capability on the bus pins provide additional application flexibility. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 4 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 6.1 Operating modes The TJA1043 supports five operating modes. Control pins STB_N and EN are used to select the operating mode. Switching between modes allows access to a number of diagnostics flags via pin ERR_N. Table 3 describes how to switch between modes. Figure 3 illustrates the mode transitions when VCC, VIO and VBAT are valid. Table 3. UVNOM[1] set cleared cleared cleared cleared cleared cleared set cleared cleared cleared cleared cleared [1] [2] [3] [4] Operating mode selection Control pins Wake[2] X X set cleared cleared X X X X set cleared X X STB_N[3] X HIGH LOW LOW LOW HIGH HIGH X HIGH LOW LOW HIGH HIGH EN X X X LOW HIGH LOW HIGH X X X X LOW HIGH Sleep mode Standby mode Standby mode Standby mode Go-to-Sleep mode[4] Listen-only mode Normal mode Sleep mode Standby mode Standby mode Sleep mode Listen-only mode Normal mode floating HIGH HIGH HIGH HIGH[4] HIGH HIGH floating HIGH HIGH floating HIGH HIGH Operating mode Pin INH UVBAT X set X X X cleared cleared X set X X cleared cleared Internal flags From Normal, Listen-only, Standby and Go-to-Sleep modes From Sleep mode Setting the UVNOM flag will clear the WAKE flag. Setting the Wake flag will clear the UVNOM flag. A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag After th(min) in Go-to-Sleep mode, the transceiver will enter Sleep mode and pin INH will be set floating. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 5 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver STB_N = H and EN = H LISTENONLY MODE STB_N = H and EN = L NORMAL MODE STB_N = H and EN = L STB_N = H and EN = L STB_N = H and EN = H STB_N = H and EN = H STB_N = L and EN = H STB_N = L and (EN = L or Wake flag set) STB_N = L and EN = L STANDBY MODE STB_N = L and EN = H and Wake flag cleared STB_N = L and EN = H and Wake flag cleared STB_N = L and (EN = L or Wake flag set) GO-TO-SLEEP MODE STB_N = H and EN = L STB_N = L and Wake flag set SLEEP MODE Wake flag cleared and t > th(min) STB_N = H and EN = H LEGEND: = H, = L logical state of pin 015aaa063 Fig 3. Mode transitions when valid VCC, VIO and VBAT voltages are present 6.1.1 Normal mode In Normal mode, the transceiver can transmit and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram). The differential receiver converts the analog data on the bus lines into digital data which is output to pin RXD. The slope of the output signals on the bus lines is controlled and optimized in a way that guarantees the lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH is active, so voltage regulators controlled by pin INH (see Figure 6) will be active too. 6.1.2 Listen-only mode In Listen-only mode, the transceiver's transmitter is disabled, effectively providing a transceiver listen-only feature. The receiver will still convert the analog bus signal on pins CANH and CANL into digital data, available for output on pin RXD. As in Normal mode, the bus pins are biased at 0.5VCC and pin INH remains active. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 6 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 6.1.3 Standby mode Standby mode is the TJA1043's first-level power saving mode, offering reduced current consumption. In Standby mode, the transceiver is unable to transmit or receive data and the low-power receiver is activated to monitor bus activity. The bus pins are biased at ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will also be active. Pins RXD and ERR_N will reflect any active wake-up requests (provided that VIO and VBAT are present). 6.1.4 Go-to-Sleep mode Go-to-Sleep mode is the controlled route for entering Sleep mode. In Go-to-Sleep mode, the transceiver behaves as in Standby mode, with the addition that a go-to-sleep command is issued to the transceiver. The transceiver will remain in Go-to-Sleep mode for the minimum hold time (th(min)) before entering Sleep mode. The transceiver will not enter Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set before th(min) has elapsed. 6.1.5 Sleep mode Sleep mode is the TJA1043's second-level power saving mode. Sleep mode is entered via Go-to-Sleep mode, and also when the undervoltage detection time on either VCC or VIO elapses before the relevant voltage level has recovered. In Sleep mode, the transceiver behaves as described for Standby mode, with the exception that pin INH is set floating. Voltage regulators controlled by this pin will be switched off, and the current into pin VBAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to wake up a node from Sleep mode (see Table 3). 6.2 Internal flags The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and system diagnosis support. Five of these flags can be polled by the controller via pin ERR_N. Which flag is available on the ERR_N at any time depends on the active operating mode and on a number of other conditions. Table 4 describes how to access these flags. Table 4. Internal flag UVNOM Accessing internal flags via pin ERR_N Flag is available on pin ERR_N[1] no Flag is cleared by setting the Pwon or Wake flags, by a LOW-to-HIGH transition on STB_N or when both VIO and VBAT have recovered. when VBAT has recovered UVBAT Pwon Wake no in Listen-only mode (coming from Standby on entering Normal mode mode, Go-to-Sleep mode, or Sleep mode) in Standby mode, Go-to-Sleep mode, and Sleep mode (provided that VIO and VBAT are present) on entering Normal mode or by setting the UVNOM flag TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 7 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver Accessing internal flags via pin ERR_N ...continued Flag is available on pin ERR_N[1] Flag is cleared Table 4. Internal flag Wake-up source Bus failure in Normal mode (before the fourth on leaving Normal mode dominant-to-recessive edge on pin TXD[2]) on re-entering Normal mode or by in Normal mode (after the fourth dominant-to-recessive edge on pin TXD[2]) setting the Pwon flag on entering Normal mode or when RXD is dominant while TXD is recessive (provided that all local failures are resolved) or by setting the Pwon flag Local failure in Listen-only mode (coming from Normal mode) [1] [2] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes. Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle. 6.2.1 UVNOM flag UVNOM is the VCC and VIO undervoltage detection flag. The flag is set when the voltage on pin VCC drops below Vuvd(VCC) for longer than tdet(uv), or when the voltage on pin VIO drops below Vuvd(VIO) for longer than tdet(uv). When the UVNOM flag is set, the transceiver enters Sleep mode to save power and to ensure the bus is not disturbed. In Sleep mode the voltage regulators connected to pin INH are disabled, avoiding any extra power consumption that might be generated as a result of a short-circuit condition. Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will clear UVNOM and the timers, allowing the voltage regulators to be reactivated (at least until UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer than trec(uv). The transceiver will then switch to the operating mode indicated by the logic levels on pins STB_N and EN (see Table 3). 6.2.2 UVBAT flag UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter Standby mode to save power and will disengage from the bus (zero load). UVBAT is cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the operating mode indicated by the logic levels on pins STB_N and EN (see Table 3). 6.2.3 Pwon flag Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers after previously dropping below Vuvd(VBAT) (usually because the battery was disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and Wake-up Source flags are set to ensure consistent system power-up under all supply conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 4). The flag is cleared when the transceiver enters Normal mode. 6.2.4 Wake flag The Wake flag is set when the transceiver detects a local or remote wake-up request. A local wake-up request is detected when the logic level on pin WAKE changes, and the new level remains stable for at least twake(min). A remote wake-up request is triggered by two bus dominant states of at least tbus(dom), with the first dominant state followed by a recessive state of at least tbus(rec) (provided the complete dominant-recessive-dominant TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 8 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver pattern is completed within tto(wake)bus). The Wake flag can be set in Standby mode, Go-to-Sleep mode or Sleep mode. Setting the Wake flag clears the UVNOM flag and timers. Once set, the Wake flag status is immediately available on pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at power-on and cleared when the UVNOM flag is set or the transceiver enters Normal mode. 6.2.5 Wake-up source flag Wake-up source recognition is provided via the Wake-up source flag, which is set when the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source flag can be polled via the ERR_N pin in Normal mode (see Table 4). This flag is also set at power-on and cleared when the transceiver leaves Normal mode. 6.2.6 Bus failure flag The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N pin in Normal mode (see Table 4). This flag is cleared at power-on or when the transceiver re-enters Normal mode. 6.2.7 Local failure flag In Normal and Listen-only modes, the transceiver can distinguish four different local failure events, any of which will cause the Local failure flag to be set. The four local failure events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping and an overtemperature event. The nature and detection of these local failures is described in Section 6.3. The Local failure flag can be polled via the ERR_N pin in Listen-only mode (see Table 4). This flag is cleared at power-on, when entering Normal mode or when RXD is dominant while TXD is recessive, provided that all local failures have been resolved. 6.3 Local failures The TJA1043 can detect four different local failure conditions. Any of these failures will set the Local failure flag, and in most cases the transmitter of the transceiver will be disabled. 6.3.1 TXD dominant clamping detection A permanent LOW level on pin TXD (due to a hardware or software application failure) would drive the CAN bus into a permanent dominant state, blocking all network communications. The TXD dominant time-out function prevents such a network lock-up by disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant time-out time tto(dom)TXD. The tto(dom)TXD timer defines the minimum possible bit rate of 40 kbit/s. The transmitter remains disabled until the Local failure flag has been cleared. 6.3.2 TXD-to-RXD short-circuit detection A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant state once it had been driven dominant, because the low-side driver of RXD is typically stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD short-circuit detection prevents such a network lock-up by disabling the transmitter. The transmitter remains disabled until the Local failure flag has been cleared. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 9 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 6.3.3 Bus dominant clamping detection A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network nodes could result in a differential voltage on the bus high enough to represent a bus dominant state. Because a node will not start transmission if the bus is dominant, the normal bus failure detection will not detect this failure, but the bus dominant clamping detection will. The Local failure flag is set if the dominant state on the bus persists for longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped bus is blocking network communications. There is no need to disable the transmitter. Note that the Local failure flag does not retain a bus dominant clamping failure, and is released as soon as the bus returns to recessive state. 6.3.4 Overtemperature detection If the junction temperature becomes excessive, the transmitter will shut down in time to protect the output drivers from overheating without compromising the maximum operating temperature. The transmitter will remain disabled until the Local failure flag has been cleared. 6.4 SPLIT pin Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see Figure 4 and Figure 6) can help to stabilize the recessive voltage level on the bus. This will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is floating. VCC TJA1043 CANH R SPLIT R CANL 60 60 VSPLIT VSPLIT = 0.5VCC in normal mode and pwon/listen-only mode; otherwise floating GND 015aaa064 Fig 4. Stabilization circuit and application 6.5 VIO supply pin Pin VIO should be connected to the microcontroller supply voltage (see Figure 6). This will cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the I/O levels of the microcontroller, facilitating direct interfacing without the need for glue logic. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 10 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 6.6 WAKE pin A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To minimize current consumption, the internal bias voltage will follow the logic state on the pin after a delay of twake(min). A HIGH level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In applications that don't make use of the local wake-up facility, it is recommended that the WAKE pin be connected to VBAT or GND to ensure optimal EMI performance. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 11 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VBAT Vx battery supply voltage voltage on pin x Conditions no time limit load dump no time limit; DC value 0 < VCC < 5.5 V on pins CANH, CANL and SPLIT no time limit; DC value on pins INH and WAKE on pins VCC, VIO, TXD, RXD, STB_N, EN, ERR_N IWAKE Vtrt VESD current on pin WAKE transient voltage electrostatic discharge voltage DC value on pins CANH, CANL, SPLIT and VBAT IEC 61000-4-2 at pins CANH and CANL HBM at pins CANH and CANL at any other pin MM at any pin CDM at corner pins at any pin Tvj Tstg [1] [2] [3] [4] [5] [6] [7] [6] [5] [1] Min -0.3 - Max +58 58 Unit V V -58 -0.3 -0.3 - +58 +58 +7 -15 V V V mA V -200 +200 [2] [3] [4] -8 -8 -4 +8 +8 +4 kV kV kV V V V C C -300 +300 -750 +750 -500 +500 [7] virtual junction temperature storage temperature -40 -55 +150 +150 Verified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 part 3 automotive transient test pulses 1, 2a, 3a and 3b. IEC 61000-4-2 (150 pF, 330 ); direct coupling. ESD performance of pins CANH and CANL according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house. The result is equal to or better than 8 kV (unaided). Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ). Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF); grade C3B. In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P x Rth(vj-a), where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 12 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 8. Thermal characteristics Table 6. Symbol Rth(vj-a) [1] Thermal characteristics Parameter thermal resistance from virtual junction to ambient Conditions in free air [1] Typ 68 Unit K/W Value is determined for free convection conditions on a JEDEC 2S2P board. 9. Static characteristics Table 7. Static characteristics VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = -40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol VCC Vuvd(VCC) ICC Parameter supply voltage undervoltage detection voltage on pin VCC supply current VBAT > 4.5 V Normal mode; VTXD = 0 V (dominant) Normal or Listen-only mode; VTXD = VIO (recessive) Standby or Sleep mode; VBAT > VCC I/O level adapter supply; pin VIO VIO Vuvd(VIO) IIO supply voltage on pin VIO undervoltage detection voltage on pin VIO supply current on pin VIO VBAT or VCC > 4.5 V Normal mode; VTXD = 0 V (dominant) Normal or Listen-only mode; VTXD = VIO (recessive) Standby or Sleep mode Supply pin VBAT VBAT Vuvd(VBAT) IBAT battery supply voltage undervoltage detection voltage on pin VBAT battery supply current Normal or Listen-only mode Standby mode; VCC > 4.5 V VINH = VWAKE = VBAT Sleep mode; VINH = VCC = VIO = 0 V; VWAKE = VBAT CAN transmit data input; pin TXD VIH VIL IIH IIL Ci HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current input capacitance VTXD = VIO Normal mode; VTXD = 0 V not tested 0.7VIO -0.3 -5 -300 0 -200 5 VIO + 0.3 V +0.3VIO +5 -30 10 V A A pF 4.5 3 15 5 5 3.5 40 18 18 40 4.3 70 30 30 V V A A A 2.8 0.8 0 0 1.8 150 1 1 5.5 2.5 500 4 4 V V A A A Conditions Min 4.5 3 30 3 0 Typ 3.5 48 6 0.75 Max 5.5 4.3 65 9 2 Unit V V mA mA A Supply pin VCC CAN receive data output; pin RXD TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 13 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver Table 7. Static characteristics ...continued VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = -40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol IOH IOL Parameter HIGH-level output current LOW-level output current Conditions VRXD = VIO - 0.4 V; VIO = VCC VRXD = 0.4 V; VTXD = VIO; bus dominant Min -12 0 Typ -6 6 Max 0 14 Unit mA mA Standby and enable control inputs; pins STB_N and EN VIH VIL IIH IIL IOH IOL IIH IIL Vth VH IL VO(dom) HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current HIGH-level output current LOW-level output current HIGH-level input current LOW-level input current threshold voltage HIGH-level voltage drop leakage current dominant output voltage VSTB_N = VEN = 0.7VIO VSTB_N = VEN = 0 V VERR_N = VIO - 0.4 V; VIO = VCC VERR_N = 0.4 V VWAKE = VBAT - 1.9 V VWAKE = VBAT - 3.1 V VSTB_N = 0 V IINH = -0.18 mA Sleep mode VTXD = 0 V; t < tto(dom)TXD pin CANH pin CANL Vdom(TX)sym VO(dif)bus transmitter dominant voltage symmetry bus differential output voltage recessive output voltage Vdom(TX)sym = VCC - VCANH - VCANL VTXD = 0 V (dominant) 45 < RL < 65 VTXD = VIO (recessive); no load VO(rec) Normal or Listen-only mode; VTXD = VIO; no load Standby or Sleep mode; no load IO(sc) short-circuit output current VTXD = 0 V (dominant); VCC = 5 V pin CANH; VCANH = 0 V pin CANL; VCANL = 40 V IO(rec) Vth(RX)dif recessive output current differential receiver threshold voltage -27 V < VCAN < 32 V Vcm(CAN) = -30 V to +30 V Normal or Listen-only mode Standby or Sleep mode Vhys(RX)dif ILI differential receiver hysteresis voltage input leakage current Normal or Listen-only mode Vcm(CAN) = -30 V to +30 V VCC = 0 V; VCANH = VCANL = 5 V VBAT = 0 V; VCANH = VCANL = 5 V TJA1043_1 All information provided in this document is subject to legal disclaimers. 0.7VIO -0.3 1 -1 -50 0.1 -10 1 VBAT - 3 0 -2 4 0 -20 0.5 -5 5 VIO + 0.3 V 0.3VIO 10 +1 -4 2 -1 10 V A A A mA A A Error and power-on indication output; pin ERR_N Local wake-up input; pin WAKE VBAT - 2.5 VBAT - 2 V 0.25 0 0.8 +2 V A Inhibit output; pin INH Bus lines; pins CANH and CANL 2.75 0.5 -400 1.5 -50 2 -0.1 -100 40 -3 [2] 3.5 1.5 0.5VCC 0 -70 70 0.7 0.7 120 170 - 4.5 2.25 +400 3.0 +50 3 +0.1 -40 100 +3 0.9 1.15 400 250 +2 V V mV V mV V V mA mA mA V V mV A A 14 of 26 0.5 0.4 [2] 50 100 -2 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver Table 7. Static characteristics ...continued VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = -40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Ri Ri Ri(dif) Ci(cm) Ci(dif) Parameter input resistance input resistance deviation differential input resistance common-mode input capacitance differential input capacitance output voltage VTXD = VCC VTXD = VCC [3] Conditions between VCANH and VCANL Min 9 -3 19 - Typ 15 0 30 - Max 28 +3 52 20 10 Unit k % k pF pF [3] Common-mode stabilization output; pin SPLIT VO Normal or Listen-only mode; -500 A < ISPLIT < 500 A Normal or Listen-only mode RL = 1 M IL leakage current Standby or Sleep mode; -58 V < VSPLIT < 58 V [3] 0.3VCC 0.45VCC -3 0.5VCC 0.5VCC 0 0.7VCC 0.55VCC +3 V V A Temperature detection Tj(sd) shutdown junction temperature 190 C [1] [2] [3] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. Vcm(CAN) is the common mode voltage of CANH and CANL. Not tested in production. 10. Dynamic characteristics Table 8. Dynamic characteristics; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = -40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device[1]. Symbol td(TXD-busdom) td(TXD-busrec) td(busrec-RXD) tPD(TXD-RXD) tdet(uv) trec(uv) tto(dom)TXD tto(dom)bus th twake(busdom) Parameter Conditions Min 40 100 1 VTXD = 0 V VO(dif)(bus) > 0.9 V from issuing go-to-sleep command to entering Sleep mode Standby or Sleep mode; VBAT = 12 V 0.3 0.3 20 0.5 Typ 70 90 60 70 0.6 0.6 35 1.75 Max 240 350 5 1.5 1.5 50 5 Unit ns ns ns ns ns ms ms ms ms s s Timing characteristics; Figure 5 delay time from TXD to bus dominant Normal mode delay time from TXD to bus recessive Normal mode delay time from bus recessive to RXD Normal or Listen-only mode propagation delay from TXD to RXD undervoltage detection time undervoltage recovery time TXD dominant time-out time bus dominant time-out time hold time bus dominant wake-up time VSTB_N = 0 V td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-only mode TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 15 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver Table 8. Dynamic characteristics; ...continued VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = -40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device[1]. Symbol twake(busrec) tto(wake)bus twake Parameter bus recessive wake-up time bus wake-up time-out time wake-up time in response to a falling or rising edge on pin WAKE; Standby or Sleep mode Conditions Standby or Sleep mode; VBAT = 12 V Min 0.5 0.5 5 Typ 1.75 25 Max 5 2 50 Unit s ms s [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. HIGH TXD LOW CANH CANL dominant 0.9 V VO(dif)(bus) 0.5 V recessive HIGH RXD 0.7VIO 0.3VIO LOW td(TXD-busdom) td(TXD-busrec) td(busdom-RXD) tPD(TXD-RXD) tPD(TXD-RXD) td(busrec-RXD) 015aaa025 Fig 5. CAN transceiver timing diagram TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 16 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 11. Application information 3V BAT 5V VBAT INH VCC VIO 10 WAKE 9 7 3 5 14 6 STB_N EN VCC Port x, y, z ERR_N RXD TXD MICROCONTROLLER RXD TXD TJA1043 GND 2 13 CANH 11 SPLIT 12 CANL 8 4 1 CAN bus wires 015aaa060 Fig 6. Typical application with 3 V microcontroller TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 17 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 12. Test information VRXD HIGH LOW hysteresis 0.5 0.9 Vi(dif)(bus) (V) mgs378 Fig 7. Hysteresis of the receiver +12 V +5 V 47 F 100 nF 5 TXD EN STB_N WAKE 1 6 14 9 VIO 3 VCC VBAT 10 13 11 12 CANH SPLIT CANL ERR_N INH RXD 15 pF GND 015aaa163 10 F RL 100 pF TJA1043 8 7 4 2 Fig 8. Test circuit for timing characteristics 12.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 18 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 A1 pin 1 index Lp 1 7 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 o 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. TJA1043_1 Package outline SOT108-1 (SO14) All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 19 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 20 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 14.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10. TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 21 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 22 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 15. Revision history Table 11. TJA1043_1 Revision history Release date 20100330 Data sheet status Product specification Change notice Supersedes Document ID TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 23 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be TJA1043_1 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 24 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1043_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 -- 30 March 2010 25 of 26 www..com NXP Semiconductors TJA1043 High-speed CAN transceiver 18. Contents 1 2 2.1 2.2 2.3 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 7 8 9 10 11 12 12.1 13 14 14.1 14.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low-power management . . . . . . . . . . . . . . . . . 1 Protection and diagnosis (detection and signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Listen-only mode . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Go-to-Sleep mode . . . . . . . . . . . . . . . . . . . . . . 7 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Internal flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Wake-up source flag. . . . . . . . . . . . . . . . . . . . . 9 Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . . 9 Local failure flag . . . . . . . . . . . . . . . . . . . . . . . . 9 Local failures . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TXD dominant clamping detection . . . . . . . . . . 9 TXD-to-RXD short-circuit detection . . . . . . . . . 9 Bus dominant clamping detection. . . . . . . . . . 10 Overtemperature detection . . . . . . . . . . . . . . . 10 SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . 10 WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Quality information . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 20 Introduction to soldering . . . . . . . . . . . . . . . . . 20 Wave and reflow soldering . . . . . . . . . . . . . . . 20 14.3 14.4 15 16 16.1 16.2 16.3 16.4 17 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 21 23 24 24 24 24 24 25 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 March 2010 Document identifier: TJA1043_1 |
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